Generally, a memory controller circuit coordinates writing and reading data to and from a memory. The data may come from a central processing unit (CPU), for example. As the capacity of memory chips increases and CPUs become faster, there is a need for data to be stored and retrieved in memory chips at increasing speeds.
FIG. 1 is a block diagram of a controller circuit 102 and a memory 104 connected together. In this example, four signals span between controller 102 and memory 104: a clock signal MCLK, a data signal PD, a command signal CMD, and a data strobe signal DQS. FIG. 2 is a timing diagram illustrating some of the challenges of writing data to a memory. In this example, command signal CMD, data signal PD, data strobe signal DQS, and clock signal MCLK are all supplied from controller circuit 102 to memory circuit 104.
In the example of FIG. 2, command signal CMD triggers a write command at the rising edge of the signal MCLK. Data strobe signal DQS oscillates on and off at some time after the write command. Memory 104 uses strobe signal DQS to “clock” or “latch” in data signal PD into memory 104 at the rising and/or falling edge of strobe signal DQS. In this example, the rising edge of strobe signal DQS is timed so that it is in the “middle” of a data bit D0 of data signal PD. For example, as shown in FIG. 2, the rising edge of strobe signal DQS occurs at a data setup time Tds after the start of bit D0, but before the end of bit D0 by the data hold time Tdh. Further, the falling edge of strobe signal DQS is timed so that it is in the “middle” of a data bit D1 of data signal PD. For example, as shown in FIG. 2, the falling edge of strobe signal DQS occurs at a data setup time Tds after the start of bit D1, but before the end of bit D1 by the data hold time Tdh.
One of the challenges of controller circuit 102 is to supply data strobe signal DQS, data signal PD, and clock signal MCLK to memory 104 with precise timing so that the data is properly latched into memory 104 without error. For example, the values of Tds and Tdh may be 0.5 nanoseconds, a very short period of time.